DESIGN CONSTRAINTS:
1)SR = 10 V/usec
2)Av = 5000 V/V
3)GB = 5 MHz
4)CL = 100 fF
5)Pdiss < 0.3 mWatt
6)ICMR+ = 1.5 Volt
7)ICMR- = 0.2 Volt
Design consideration:
We consider that
1)10uA current flows through 1st stage
2)20uA current flows through the next stage
3)A cascoded current mirror it used for realizing the current source( vary its W/L to get 20uA and 10uA currents resp).
TECHNOLOGY USED: 180nm technology
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corresponding AC analysis gives:
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This is the Mag-Phase plot for (0-10^12)Hz frequency range.
Problems Encountered:
1) Regarding phase plot:
Between (10^8- 10^9),in the magnitude curve, we have a - 40dB slope(due to presence of poles) .There after we have a zero. So theoretically there should be a positive slope for the phase plot (due to the presence of zero), though no such thing can be observed from the simulation result.
2) Regarding frequency compensation:
Variation in R and Cc is not giving much difference in the frequency response (phase margin).