1)SR = 10 V/usec
2)Av = 5000 V/V
3)GB = 5 MHz
4)CL = 100 fF
5)Pdiss < 0.3 mWatt
6)ICMR+ = 1.5 Volt
7)ICMR- = 0.2 Volt
Design consideration:
We consider that
1)10uA current flows through 1st stage
2)20uA current flows through the next stage
3)A cascoded current mirror it used for realizing the current source( vary its W/L to get 20uA and 10uA currents resp).
TECHNOLOGY USED: 180nm technology
corresponding AC analysis gives:
This is the Mag-Phase plot for (0-10^12)Hz frequency range.Problems Encountered:
1) Regarding phase plot:
Between (10^8- 10^9),in the magnitude curve, we have a - 40dB slope(due to presence of poles) .There after we have a zero. So theoretically there should be a positive slope for the phase plot (due to the presence of zero), though no such thing can be observed from the simulation result.
2) Regarding frequency compensation:
Variation in R and Cc is not giving much difference in the frequency response (phase margin).
I am designing a two stage op amp for the following specifications while driving a load of CL = 15 pF:
ReplyDeleteA unity-gain frequency (ft) of 300 kHz or greater.
A low-frequency gain of 72 dB or greater.
A phase margin of at least 60°.
A power dissipation of 16 mW or less.
An input common-mode range (ICMR) and output common-mode range (OCMR) of ±1V, with no visible distortion of signals between these values.
A layout that fits within a 220μm × 220μm square. The 15-pF load capacitor CL should not be included in your layout, and should only be included in your simulation, as this represents an external load.
Use gpdk 80 nm n-well CMOS process
High-speed op-amp. Circuits will be judged on unity-gain frequency. Any circuit entered in this area also must have positive and negative slew rates greater than 30 V/μs.
HOW DO YOU CALCULATE THE W/L RATIOS OF THE TRANSISTORS?????
hi,
ReplyDeletei'm trying to replicate your circuit.
could you please elaborate more on how the ac analysis was carried out?
you could email me at
ashwath.krishnan7@gmail.com
the reason why thers no positive slope is because the poles are compensated.
ReplyDeletesend design of 3 stage opamp
ReplyDeletecan u pls help me in getting the values of the W/L of the transistors in this design of 2 stage opamp????
ReplyDelete(https://docs.google.com/drawings/d/1CpON116m69ylzwMGJiLHVjsJBYcLNASsZPXH2j9pFJA/edit)
180nm technology is used.. and more than 60 dB is required. unity gain Freq is 120MHz for cap load of 2pF. power supply is 1.5V.
my mail id is megan.starofdavid@gmail.com!!!
thank u!!!
can u mail me w/l ratios
ReplyDeletemail id is naveensigroha1991@gmail.com